
module riscv_regfile(
	input rst, 		//复位信号，下降沿触发，低电平有效
	input clk,		//时钟信号
	input we,		//写信号, 高有效
	input [4:0] rs1,  	//第一个source register的id
	input [4:0] rs2, 	//第二个source register的id
	input [4:0] rd,		//destination register的id
	input [31:0] data_in,	//写入的destination register的数据
	output [31:0] data_out1, // 从第一个src register读出的数据
	output [31:0] data_out2	 // 从第二个src register读出的数据
);

integer i;

reg [31:0] x[1:31];
reg [31:0] r1;		//output reg1
reg [31:0] r2;		//output reg2

always @(negedge clk) begin
    if (!rst) begin
		for (i = 1; i <= 31; i = i + 1)
			x[i] =32'h0000_0000;
    end else if (we == 1'b1) begin
        x[rd] <= data_in;
    end
end //always

always @(*) begin
    if (rs1 == 0) begin
        r1 = 32'h0000_0000;
    end else begin
        r1 = x[rs1];
    end

    if (rs2 == 0) begin
        r2 = 32'h0000_0000;
    end else begin
        r2 = x[rs2];
    end
end // always @(*)

assign data_out1 = r1;
assign data_out2 = r2;

endmodule

